Recognition of digital logic circuit diagrams

When designing digital logic circuits, it is frequently necessary to draw the circuits by hand before implementing the design in RTL. If there are some issues faced during simulation or synthesis of the design, the design process has to be repeated. To speed up the design cycle, it would be beneficial to have an environment that can capture handdrawn digital circuit diagrams and generate the RTL code for the logic. The Verilog RTL code generated by the environment can be used directly in simulation and synthesis environments.